发明申请
US20050104116A1 Stacked gate memory cell with erase to gate, array, and method of manufacturing
有权
具有擦除到栅极，阵列和制造方法的堆叠栅极存储单元
- 专利标题： Stacked gate memory cell with erase to gate, array, and method of manufacturing
- 专利标题（中）： 具有擦除到栅极，阵列和制造方法的堆叠栅极存储单元
-
申请号： US10714243申请日： 2003-11-13
-
公开(公告)号： US20050104116A1公开(公告)日： 2005-05-19
- 发明人: Bomy Chen , Hieu Tran , Dana Lee , Jack Frayer
- 申请人： Bomy Chen , Hieu Tran , Dana Lee , Jack Frayer
- 主分类号： G11C16/04
- IPC分类号： G11C16/04 ; H01L21/8247 ; H01L27/115 ; H01L29/788
摘要：
A stacked gate nonvolatile memory floating gate device has a control gate. Programming of the cell in the array is accomplished by hot channel electron injection from the drain to the floating gate. Erasure occurs by Fowler-Nordheim tunneling of electrons from the floating gate to the control gate. Finally, to increase the density, each cell can be made in a trench.
公开/授权文献
信息查询
