发明申请
- 专利标题: Highly parallel switching systems utilizing error correction
- 专利标题(中): 高度并行的开关系统利用纠错
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申请号: US10976132申请日: 2004-10-27
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公开(公告)号: US20050105515A1公开(公告)日: 2005-05-19
- 发明人: Coke Reed , David Murphy
- 申请人: Coke Reed , David Murphy
- 申请人地址: US NY New York 10022
- 专利权人: Interactic Holdings, LLC
- 当前专利权人: Interactic Holdings, LLC
- 当前专利权人地址: US NY New York 10022
- 主分类号: G06F
- IPC分类号: G06F20060101 ; H04L1/00 ; H04L12/50 ; H04L12/56
摘要:
An interconnect structure comprises a logic capable of error detection and/or error correction. A logic formats a data stream into a plurality of fixed-size segments. The individual segments include a header containing at least a set presence bit and a target address, a payload containing at least segment data and a copy of the target address, and a parity bit designating parity of the payload, the logic arranging the segment plurality into a multiple-dimensional matrix. A logic analyzes segment data in a plurality of dimensions following passage of the data through a plurality of switches including analysis to detect segment error, column error, and payload error.