- 专利标题： Memory cache bank prediction
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申请号： US11045528申请日： 2005-01-28
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公开(公告)号： US20050132138A1公开(公告)日： 2005-06-16
- 发明人: Adi Yoaz , Ronny Ronen , Lihu Rappoport , Mattan Erez , Stephan Jourdan , Bob Valentine
- 申请人： Adi Yoaz , Ronny Ronen , Lihu Rappoport , Mattan Erez , Stephan Jourdan , Bob Valentine
- 主分类号： G06F9/38
- IPC分类号： G06F9/38 ; G06F12/08 ; G06F12/00
摘要：
A memory cache bank prediction unit is provided for use in a processor having a plurality of memory cache banks. The memory cache bank prediction unit has an input port that receives an instruction. The memory cache bank prediction unit also has an evaluation unit, coupled to the input port, that predicts which of the plurality of memory cache banks is associated with the instruction.
公开/授权文献
- US07644236B2 Memory cache bank prediction 公开/授权日：2010-01-05
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