发明申请
US20050151160A1 On-chip structure for electrostatic discharge (ESD) protection
失效
用于静电放电（ESD）保护的片上结构
- 专利标题： On-chip structure for electrostatic discharge (ESD) protection
- 专利标题（中）： 用于静电放电（ESD）保护的片上结构
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申请号： US11032154申请日： 2005-01-11
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公开(公告)号： US20050151160A1公开(公告)日： 2005-07-14
- 发明人: Javier Salcedo , Juin Liou , Joseph Bernier , Donald Whitney
- 申请人： Javier Salcedo , Juin Liou , Joseph Bernier , Donald Whitney
- 专利权人： Intersil Americas Inc.,The University of Central Florida
- 当前专利权人： Intersil Americas Inc.,The University of Central Florida
- 主分类号： H01L27/02
- IPC分类号： H01L27/02 ; H01L29/72
摘要：
A complementary SCR-based structure enables a tunable holding voltage for robust and versatile ESD protection. The structure are n-channel high-holding-voltage low-voltage-trigger silicon controller rectifier (N-HHLVTSCR) device and p-channel high-holding-voltage low-voltage-trigger silicon controller rectifier (P-HHLVTSCR) device. The regions of the N-HHLVTSCR and P-HHLVTSCR devices are formed during normal processing steps in a CMOS or BICMOS process. The spacing and dimensions of the doped regions of N-HHLVTSCR and P-HHLVTSCR devices are used to produce the desired characteristics. The tunable HHLVTSCRs makes possible the use of this protection circuit in a broad range of ESD applications including protecting integrated circuits where the I/O signal swing can be either within the range of the bias of the internal circuit or below/above the range of the bias of the internal circuit.
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