A receiver circuit arrangement contains a receiver circuit (2) having an input (201) for receiving an input signal (IN), having an output (202) for outputting an output signal (OUT_F) and having an inverter circuit (21, 22, 23) having switching transistors (211, 212), to which the input signal is fed, at least one control transistor (221, 222) being connected in series with the switching transistors. A control circuit (3) is connected, on the input side, to a terminal for a reference voltage (VREF) and, on the output side, to the control terminal of the control transistor (221, 222) of the inverter circuit. The control circuit (3) is designed in such a way that the control transistor (221, 222) is driven by the regulating switching circuit in the event of deviations of the reference voltage (VREF) from a voltage value in a reference operating state with a control voltage (VCTL1, VCTL2) that deviates with respect to the reference operating state. The receiver circuit arrangement is comparatively insensitive to fluctuations of a reference voltage with respect to a nominal value of a reference operating state and enables high switching speeds.