- 专利标题： Package design and method of manufacture for chip grid array
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申请号： US11128014申请日： 2005-05-12
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公开(公告)号： US20050205987A1公开(公告)日： 2005-09-22
- 发明人: Tan Hwee , Roman Perez , Kee Lau , Alex Chew , Antonio Dimaano
- 申请人： Tan Hwee , Roman Perez , Kee Lau , Alex Chew , Antonio Dimaano
- 专利权人： ADVANPACK SOLUTIONS PTE. LTD.
- 当前专利权人： ADVANPACK SOLUTIONS PTE. LTD.
- 主分类号： H01L23/31
- IPC分类号： H01L23/31 ; H01L23/36 ; H01L23/02 ; H01L23/48 ; H01L23/52 ; H01L29/40
摘要：
A chip level package utilizing a CGA is described. A semiconductor chip with pillars is molded in an encapsulant. Solder balls are added and connected to the chip pillars. The final package does not require a first level substrate or interposer and is able to be assembled to the next level as is. An additional embodiment describes the addition of a thermal heat sink to the packaged chip.
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