发明申请
- 专利标题: Semiconductor device manufacturing method
- 专利标题(中): 半导体器件制造方法
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申请号: US11030042申请日: 2005-01-07
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公开(公告)号: US20050208427A1公开(公告)日: 2005-09-22
- 发明人: Katsuya Hayano , Norio Hasegawa
- 申请人: Katsuya Hayano , Norio Hasegawa
- 优先权: JP2004-073739 20040316
- 主分类号: G03F1/30
- IPC分类号: G03F1/30 ; G03F1/32 ; G03F1/56 ; G03F1/68 ; G03F7/00 ; G03F7/20 ; H01L21/027 ; H01L21/30 ; H01L21/768
摘要:
A semiconductor device manufacturing method which shortens the turnaround time for semiconductor devices. In this method, shading material of resist film lies over a main surface of mask blanks and light-transmitting patterns are made as openings in the shading material. A planarizing film is formed so as to cover the shading material and phase shifters of resist film are formed on the flat top surface of the planarizing film. For exposure, pattern is used. Multiple exposure with two or more exposure areas is made in one chip area, where the exposure areas have patterns equal in shape, size, and arrangement, and phase shifters arranged alternately, so that a line pattern is transferred onto a positive type photoresist film of a semiconductor wafer.
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