发明申请
US20050210431A1 INTEGRATED CIRCUIT DESIGN FOR SIGNAL INTEGRITY, AVOIDING WELL PROXIMITY EFFECTS
失效
集成电路设计信号完整性，避免良性接近效应
- 专利标题： INTEGRATED CIRCUIT DESIGN FOR SIGNAL INTEGRITY, AVOIDING WELL PROXIMITY EFFECTS
- 专利标题（中）： 集成电路设计信号完整性，避免良性接近效应
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申请号： US10708715申请日： 2004-03-19
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公开(公告)号： US20050210431A1公开(公告)日： 2005-09-22
- 发明人: Karen Bard , Ronald Rose , Michael Sitko
- 申请人： Karen Bard , Ronald Rose , Michael Sitko
- 申请人地址： US NY Armonk
- 专利权人： INTERNATIONAL BUSINESS MACHINES CORPORATION
- 当前专利权人： INTERNATIONAL BUSINESS MACHINES CORPORATION
- 当前专利权人地址： US NY Armonk
- 主分类号： G06F9/45
- IPC分类号： G06F9/45 ; G06F17/50 ; H01L27/02
摘要：
A method, system and program product for designing an integrated circuit (IC) for signal integrity. The invention conducts a signal integrity analysis on an IC design; identifies any field effect transistor (FET) that causes a signal integrity failure in the case that the IC design fails the signal integrity analysis; and modifies an edge of a failing FET that is closer than a threshold distance to a well edge. The invention eliminates the manual, iterative procedure for determining the device causing a signal integrity failure due to well proximity effects.
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