A semiconductor integrated circuit device includes a memory cell array, an address transition detecting circuit which detects transition of a column address signal, the column address signal being used to specify a column address of the memory cell array, a control circuit having a timeout circuit, the control circuit which generates an internal circuit control signal of desired length used to control column access to the memory cell array based on a result of detection by the address transition detecting circuit, and a column selection line whose selection time is controlled by the control circuit, wherein the column address signal used for selection of the column selection line is latched in a period of time in which the column selection line is selected at a write operation time.