发明申请
- 专利标题： Reduced data line pre-fetch scheme
- 专利标题（中）： 减少数据线预取方案
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申请号： US11207919申请日： 2005-08-19
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公开(公告)号： US20050276104A1公开(公告)日： 2005-12-15
- 发明人: Todd Merritt , Donald Morgan
- 申请人： Todd Merritt , Donald Morgan
- 主分类号： G11C7/10
- IPC分类号： G11C7/10 ; G11C11/34 ; G11C11/4096
摘要：
A memory device for reducing the number of data read lines needed in a memory device. Specifically, multiple helper flip-flops are used to prefetch data in a memory device. The helper flip-flops are configured to latch one or two of the data bits from a 4-bit prefetch in an alternating periodic fashion, thereby necessitating fewer data lines.
公开/授权文献
- US07142443B2 Reduced data line pre-fetch scheme 公开/授权日：2006-11-28
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