A memory package and a chip architecture which includes stacked multiple memory chips is described. In a first aspect, a memory package comprises a substrate and a plurality of memory dies mounted on the substrate. Each die has a separate chip enable. In a second aspect, a chip architecture comprises a printed circuit board (PCB). The PCB includes a footprint. The footprint includes at least one no connect (NC) pad. The chip architecture includes a plurality of stacked memory chips mounted on the printed circuit board. Each of the plurality of stacked memory has a chip enable signal pin and also has at least one NC pin. At least one of the plurality of stacked memory chips utilizes an NC pin of another of the stacked memory chips to route the chip enable pin to at least one NC pad of the footprint. Accordingly, a system and method in accordance with the present invention provides for increased memory density within a particular space constraint by (1) providing multiple dies in a single memory package and (2) by providing stacked memory chips in a single PCB footprint. In so doing, the package/PCB will have increased memory density over a conventional package/PCB within the same space constraints, and the capacity of Flash storage devices is expanded accordingly.