Invention Application
- Patent Title: High voltage FET gate structure
- Patent Title (中): 高压FET栅极结构
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Application No.: US11138888Application Date: 2005-05-26
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Publication No.: US20060001050A1Publication Date: 2006-01-05
- Inventor: Bin Wang , Chih-Hsin Wang
- Applicant: Bin Wang , Chih-Hsin Wang
- Applicant Address: US WA Seattle 98103
- Assignee: IMPINJ, Inc.
- Current Assignee: IMPINJ, Inc.
- Current Assignee Address: US WA Seattle 98103
- Main IPC: H01L29/745
- IPC: H01L29/745 ; H01L21/335

Abstract:
A FET device for operation at high voltages includes a substrate, a first well and a second well within the substrate that are doped with implants of a first type and second type, respectively. The first and second wells define a p-n junction. A field oxide layer within the second well defines a first surface region to receive a drain contact. A third well is located at least partially in the first well, includes doped implants of the second type, and is adapted to receive a source contact. As such, the third well defines a channel between itself and the second well within the first well. A gate is disposed over the channel. At least a first portion of the gate is disposed over the p-n junction, and includes doped implants of the first type. A number of permutations are allowed for doping the remainder of the gate.
Public/Granted literature
- US07375398B2 High voltage FET gate structure Public/Granted day:2008-05-20
Information query
IPC分类: