- 专利标题: Programmable logic devices with multi-standard byte synchronization and channel alignment for communication
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申请号: US11189209申请日: 2005-07-26
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公开(公告)号: US20060012394A1公开(公告)日: 2006-01-19
- 发明人: Ramanand Venkata , Chong Lee , Rakesh Patel
- 申请人: Ramanand Venkata , Chong Lee , Rakesh Patel
- 专利权人: Altera Corporation
- 当前专利权人: Altera Corporation
- 主分类号: H03K19/177
- IPC分类号: H03K19/177
摘要:
A programmable logic device (“PLD”) includes communication interface circuitry that can support any of a wide range of communication protocols, including Packet Over Sonet (“POS-5”) and 8-bit/10-bit (“8B10B”) protocols. The interface circuitry includes various functional blocks that are at least partly hard-wired to perform particular types of functions, but that in at least many cases are also partly programmable to allow the basic functions to be adapted for various protocols. Routing of signals to, from, between, and/or around the various functional blocks is also preferably at least partly programmable to facilitate combining the functional blocks in various ways to support various protocols.