发明申请
- 专利标题: Semiconductor device, memory device and memory module having digital interface
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申请号: US10982946申请日: 2004-11-08
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公开(公告)号: US20060018407A1公开(公告)日: 2006-01-26
- 发明人: Hideki Osaka , Yoji Nishio , Seiji Funaba , Kazuyoshi Shoji
- 申请人: Hideki Osaka , Yoji Nishio , Seiji Funaba , Kazuyoshi Shoji
- 优先权: JP2004-217509 20040726
- 主分类号: H03K9/00
- IPC分类号: H03K9/00
摘要:
An object of the present invention is to reduce jitter dependent on data patterns by an interface receiver. Another object of the present invention is to provide an LSI capable of automatically adjusting a delay time for jitter reduction so as to be able to control its setting for each device. Since the jitter dependent on the data patterns can be expected according to how the previous state is being placed, the state of data received by the receiver is held, and the timing provided to fetch input data is adjusted according to the held state and the input data. As a control mechanism lying in the receiver, for determining a delay time dependent on the form of mounting, a driver transmits and receives pulse data set at one-cycle intervals and pulse data set at two-cycle intervals as test patterns. The receiver has an automatic control mechanism for determining a delay time optimal to a system from the difference between a rising time of each of pulses different in pulse width and its falling time.
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