- 专利标题： Transistor fabrication methods using reduced width sidewall spacers
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申请号： US10899359申请日： 2004-07-26
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公开(公告)号： US20060019455A1公开(公告)日： 2006-01-26
- 发明人: Haowen Bu , PR Chidambaram , Rajesh Khamankar
- 申请人： Haowen Bu , PR Chidambaram , Rajesh Khamankar
- 主分类号： H01L21/336
- IPC分类号： H01L21/336
摘要：
Transistor fabrication methods (50) are presented in which shrinkable sidewall spacers (120) are formed (66, 68) along sides of a transistor gate (114), and a source/drain implant is performed (74) after forming the sidewall spacer (120). The sidewall spacer width is then reduced by annealing the shrinkable sidewall spacer material (76) following the source/drain implant (74).
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