发明申请
US20060024927A1 Methods of forming a P-well in an integrated circuit device 失效
在集成电路器件中形成P阱的方法

  • 专利标题: Methods of forming a P-well in an integrated circuit device
  • 专利标题(中): 在集成电路器件中形成P阱的方法
  • 申请号: US10899596
    申请日: 2004-07-27
  • 公开(公告)号: US20060024927A1
    公开(公告)日: 2006-02-02
  • 发明人: Ranadeep DuttaFrank Thiel
  • 申请人: Ranadeep DuttaFrank Thiel
  • 主分类号: H01L21/425
  • IPC分类号: H01L21/425
Methods of forming a P-well in an integrated circuit device
摘要:
The present invention is generally directed to a method of forming a p-well in an integrated circuit device. In one illustrative embodiment, the method comprises forming a first layer of epitaxial material above an active layer of a substrate, forming a first doped region in the first layer of epitaxial material, forming a second layer of epitaxial material above the first layer of epitaxial material, forming a second doped region in the second layer of epitaxial material, and performing at least one heat treating process.
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