发明申请
- 专利标题: Error correcting logic system
- 专利标题(中): 错误校正逻辑系统
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申请号: US10710641申请日: 2004-07-27
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公开(公告)号: US20060026457A1公开(公告)日: 2006-02-02
- 发明人: Kerry Bernstein , Philip Emma , John Fifield , Paul Kartschoke , William Klaasen , Norman Rohrer
- 申请人: Kerry Bernstein , Philip Emma , John Fifield , Paul Kartschoke , William Klaasen , Norman Rohrer
- 申请人地址: US NY Armonk
- 专利权人: International Business Machines Corporation
- 当前专利权人: International Business Machines Corporation
- 当前专利权人地址: US NY Armonk
- 主分类号: G06F11/00
- IPC分类号: G06F11/00
摘要:
The invention includes an error correcting logic system that allows critical circuits to be hardened with only one redundant unit and without loss of circuit performance. The system provides an interconnecting gate that suppresses a fault in one of at least two redundant dynamic logic gates that feed to the interconnecting gate. The system is applicable to dynamic or static logic systems. The system prevents propagation of a fault, and addresses not only soft errors, but noise-induced errors.
公开/授权文献
- US07336102B2 Error correcting logic system 公开/授权日:2008-02-26