An EEPROM cell includes first and second assist gates on opposite sides of a charge retaining insulating layer. Current in the EEPROM memory cell flows between inversion layers, which are created in response to a bias applied to the assist gates. The insulating layer can include silicon nitride, which is provided between layers of silicon dioxide above the channel region, such that these layers can constitute a dielectric stack, which can be fabricated to occupy a relatively small area.