发明申请
US20060035460A1 Wiring structure for integrated circuit with reduced intralevel capacitance
有权
具有降低的体积电容的集成电路的接线结构
- 专利标题： Wiring structure for integrated circuit with reduced intralevel capacitance
- 专利标题（中）： 具有降低的体积电容的集成电路的接线结构
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申请号： US11203944申请日： 2005-08-15
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公开(公告)号： US20060035460A1公开(公告)日： 2006-02-16
- 发明人: Richard Wise , Bomy Chen , Mark Hakey , Hongwen Yan
- 申请人： Richard Wise , Bomy Chen , Mark Hakey , Hongwen Yan
- 主分类号： H01L21/4763
- IPC分类号： H01L21/4763
摘要：
A method of forming a wiring structure for an integrated circuit includes the steps of forming a plurality of features in a layer of dielectric material, and forming spacers on sidewalls of the features. Conductors are then formed in the features, being separated from the sidewalls by the spacers. The spacers are then removed, forming air gaps at the sidewalls so that the conductors are separated from the sidewalls by the air gaps. Dielectric layers above and below the conductors may be low-k dielectrics having a dielectric constant less than that of the dielectric between the conductors. A cross-section of each of the conductors has a bottom in contact with the a low-k dielectric layer, a top in contact with another low-k dielectric, and sides in contact only with the air gaps. The air gaps serve to reduce the intralevel capacitance.
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