发明申请
US20060043531A1 Reduction of source and drain parasitic capacitance in CMOS devices
审中-公开
降低CMOS器件中的源极和漏极寄生电容
- 专利标题： Reduction of source and drain parasitic capacitance in CMOS devices
- 专利标题（中）： 降低CMOS器件中的源极和漏极寄生电容
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申请号： US10928555申请日： 2004-08-27
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公开(公告)号： US20060043531A1公开(公告)日： 2006-03-02
- 发明人: Yuri Erokhin , Ukyo Jeong , Jay Scheuer , Steven Walther
- 申请人： Yuri Erokhin , Ukyo Jeong , Jay Scheuer , Steven Walther
- 申请人地址： US MA Gloucester
- 专利权人： Varian Semiconductor Equipment Associates, Inc.
- 当前专利权人： Varian Semiconductor Equipment Associates, Inc.
- 当前专利权人地址： US MA Gloucester
- 主分类号： H01L29/788
- IPC分类号： H01L29/788
摘要：
A method for fabricating a semiconductor-based device includes providing a doped semiconductor substrate, introducing a second dopant into the substrate to define a pn junction, and introducing a neutralizing species into the substrate in the neighborhood of the pn junction to reduce a capacitance associated with the pn junction. A semiconductor-based device includes a semiconductor substrate having first and second dopants, and a neutralizing species. The first and second dopants define a pn junction, and the neutralizing species neutralizes a portion of the first dopant in the neighborhood of the pn junction to decrease a capacitance associated with the pn junction.
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