- 专利标题: Method of manufacturing a semiconductor integrated circuit device
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申请号: US11265292申请日: 2005-11-03
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公开(公告)号: US20060057795A1公开(公告)日: 2006-03-16
- 发明人: Hiraku Chakihara , Mitsuhiro Noguchi , Masahiro Tadokoro , Naonori Wada , Akio Nishida
- 申请人: Hiraku Chakihara , Mitsuhiro Noguchi , Masahiro Tadokoro , Naonori Wada , Akio Nishida
- 优先权: JP2003-153882 20030530
- 主分类号: H01L21/8234
- IPC分类号: H01L21/8234
摘要:
In forming five trenches buried with an intermediate conductive layer for connecting transfer MISFETs and driving MISFETs with vertical MISFETs formed thereover, in which the second and third trenches, and the first, fourth, and fifth trenches are formed separately by twice etching using first and second photoresist films as a mask. Since all the trenches can be formed at a good accuracy even in a case where the shortest distance between the first trench and the second or third trench, and the shortest distance between the second or third trench and the fourth trench is smaller than the resolution limit for the exposure light, the distance between each of the five trenches arranged in one identical memory cell can be reduced to be smaller than resolution limit for the exposure light.
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