Invention Application
- Patent Title: Semiconductor memory having electrically erasable and programmable semiconductor memory cells
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Application No.: US11206995Application Date: 2005-08-19
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Publication No.: US20060062045A1Publication Date: 2006-03-23
- Inventor: Kunihiro Katayama , Takayuki Tamura , Kiyoshi Inoue
- Applicant: Kunihiro Katayama , Takayuki Tamura , Kiyoshi Inoue
- Priority: JP09-139019 19970528
- Main IPC: G11C16/04
- IPC: G11C16/04

Abstract:
An electrically alterable non-volatile multi-level memory device and a method of operating such a device, which includes setting a status of at least one of the memory cells to one state selected from a plurality of states including at least first to fourth level states, in response to information to be stored in the one memory cell, and reading the status of the memory cell to determine whether the read out status corresponds to one of the first to fourth level states by utilizing a first reference level set between the second and third level states, a second reference level set between the first and second level states and a third reference level set between the third and fourth level states.
Public/Granted literature
- US07295467B2 Semiconductor memory having electrically erasable and programmable semiconductor memory cells Public/Granted day:2007-11-13
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