- 专利标题: Doped polysilicon via connecting polysilicon layers
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申请号: US10955710申请日: 2004-09-29
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公开(公告)号: US20060071074A1公开(公告)日: 2006-04-06
- 发明人: Michael Konevecki , Usha Raghuram , Maitreyee Mahajani , Sucheta Nallamothu , Andrew Walker , Tanmay Kumar
- 申请人: Michael Konevecki , Usha Raghuram , Maitreyee Mahajani , Sucheta Nallamothu , Andrew Walker , Tanmay Kumar
- 申请人地址: US CA Santa Clara
- 专利权人: Matrix Semiconductor, Inc.
- 当前专利权人: Matrix Semiconductor, Inc.
- 当前专利权人地址: US CA Santa Clara
- 主分类号: G06K7/10
- IPC分类号: G06K7/10
摘要:
The invention provides for polysilicon vias connecting conductive polysilicon layers formed at different heights. Polysilicon vias are advantageously used in a monolithic three dimensional memory array of charge storage transistors. Polysilicon vias according to the present invention can be used, for example, to connect the channel layer of a first device level of charge storage transistor memory cells to the channel layer of a second device layer of such cells formed above the first device level. Similarly, vias according to the present invention can be used to connect the wordline of a first device level of charge storage transistor memory cells to the channel layer of a second device layer of such cells.
公开/授权文献
- US07566974B2 Doped polysilicon via connecting polysilicon layers 公开/授权日:2009-07-28
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