A clock generator and method of generating a spread spectrum clock (SSC) signal, in which a delay cell array (DCA) control signal may be output based on one of a received spread spectrum clock generator (SSCG) signal and a feedback signal. The SSC signal may be generated based on at least one of the DCA control signal and a plurality of path control signals. Modulation properties of the SSC signal may be controlled based on a plurality of path control signals.