发明申请
- 专利标题: Method for reducing semiconductor die warpage
- 专利标题(中): 降低半导体模具翘曲的方法
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申请号: US11252990申请日: 2005-10-18
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公开(公告)号: US20060094208A1公开(公告)日: 2006-05-04
- 发明人: Seung Park , Tae Lee , Hyun Park
- 申请人: Seung Park , Tae Lee , Hyun Park
- 申请人地址: US CA Fremont
- 专利权人: ChipPAC, Inc
- 当前专利权人: ChipPAC, Inc
- 当前专利权人地址: US CA Fremont
- 主分类号: H01L21/78
- IPC分类号: H01L21/78
摘要:
An anti-warpage backgrinding tape (11) is secured to the circuit side (12) of a semiconductor wafer (14). The backside (16) of the wafer is background. The backside of the wafer is secured to dicing tape (18) so that the anti-warpage backgrinding tape is exposed. The wafer is diced to create individual die structure (34). The die structure comprises semiconductor die (22) with anti-warpage tape elements (36) on circuit sides of the semiconductor die. A die structure is removed from the dicing tape. The backside of the die of the die structure is adhered to a substrate (24). The anti-warpage tape element is removed from the die. The anti-warpage backgrinding tape is preferably partially or fully transparent to permit sensing of guide markings on the wafer during wafer dicing. The adhesive is preferably a curable adhesive. The adhesion between the anti-warpage tape element and the chosen die may be reduced by the application of heat (38).
公开/授权文献
- US07256108B2 Method for reducing semiconductor die warpage 公开/授权日:2007-08-14
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