Invention Application
- Patent Title: Methods of forming planarized multilevel metallization in an integrated circuit
- Patent Title (中): 在集成电路中形成平面化多层金属化的方法
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Application No.: US10976539Application Date: 2004-10-29
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Publication No.: US20060094232A1Publication Date: 2006-05-04
- Inventor: Chin-Ta Su , Jerry Lai , Yu-Lin Yen
- Applicant: Chin-Ta Su , Jerry Lai , Yu-Lin Yen
- Main IPC: H01L21/4763
- IPC: H01L21/4763

Abstract:
A method is provided for forming a semiconductor device that reduces metal-stress-induced photo misalignment by incorporating a multi-layered anti-reflective coating over a metal layer. The method includes providing a substrate with a conductive layer formed over the substrate, depositing a multi-layered anti-reflective coating (including alternating layers of titanium and titanium nitride), defining a plurality of conductive lines in connection with a first etching step, depositing a dielectric layer, and defining at least one via in connection with a second etching step.
Public/Granted literature
- US07314813B2 Methods of forming planarized multilevel metallization in an integrated circuit Public/Granted day:2008-01-01
Information query
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