In one embodiment, an interface facilitates communication of data between a source block and a sink block. The interface comprises a first register element that receives data from the source block via an input line, wherein the first register element changes value when a clock enable signal is applied to the first register element and maintains its value when the clock enable signal is not applied; a first multiplexer coupled to the input line and an output of the first register element; and a first shift register for receiving a signal from the sink block indicating that the sink block is retrieving data from the interface; wherein the first shift register outputs a delayed version of the signal from the sink block to provide the clock enable signal to the first register element and to control an output of the first multiplexer.