A process for the definition of integrated circuits on a wafer having at least one silicon semiconductor layer includes masking the wafer with a photoresist layer. The process includes a development step of the photoresist with definition of a lithographic pattern, a hardening step of the photoresist with a plasma of inert gas, and a dry etching step with a plasma of reactive gas for transferring the lithographic pattern on the wafer. The dry etching step includes at least an initial step, or breakthrough, with a plasma of a chlorinated gas and of an inert gas for removal of a silicon native oxide grown on the wafer.