- 专利标题: Memory arrangement with low power consumption
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申请号: US11259573申请日: 2005-10-26
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公开(公告)号: US20060120124A1公开(公告)日: 2006-06-08
- 发明人: Siddharth Gupta , Yannick Martelloni
- 申请人: Siddharth Gupta , Yannick Martelloni
- 优先权: DE102004052218.9 20041027
- 主分类号: H02M7/04
- IPC分类号: H02M7/04
摘要:
A memory arrangement, particularly a ROM, having memory cells, local virtual supply voltage lines, word lines and result lines may also include global virtual supply voltage lines that run along the width of the memory arrangement parallel to the word lines. The local virtual supply voltage lines run parallel to the result lines, and perpendicularly to the word lines where the each local virtual supply voltage line runs only within a block of the memory arrangement. Each global virtual supply voltage line, in each block through which it runs, is connected to one local virtual supply voltage line. The coupling capacitance between the supply voltage lines and the result lines, and the inherent capacitance of the supply voltage lines are reduced, reducing the power consumption and increasing the clock frequency of the memory arrangement.
公开/授权文献
- US07508691B2 Memory arrangement with low power consumption 公开/授权日:2009-03-24