发明申请
- 专利标题: MEMORY ARRAY WITH FAST BIT LINE PRECHARGE
- 专利标题(中): 存储器阵列与快速位线预置
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申请号: US11004148申请日: 2004-12-03
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公开(公告)号: US20060120175A1公开(公告)日: 2006-06-08
- 发明人: Sheree Chou , Yung-Feng Lin , Yu-Shen Lin
- 申请人: Sheree Chou , Yung-Feng Lin , Yu-Shen Lin
- 申请人地址: TW Hsinchu
- 专利权人: Macronix International Co., Ltd.
- 当前专利权人: Macronix International Co., Ltd.
- 当前专利权人地址: TW Hsinchu
- 主分类号: G11C7/10
- IPC分类号: G11C7/10
摘要:
An integrated circuit memory array with an extra column of memory cells and a reference bit line is provided, in which the reference bit line acts as a reference for a shared precharging and clamping control on the bit lines in the array. Precharge transistors are coupled to respective bit lines in the array, and adapted to precharge voltage on the respective bit lines to near a target level. A detector has an input coupled to the reference bit line and an output coupled to the precharge transistors on the plurality of bit lines. The detector generates a precharge signal which turns off the precharge transistors when the reference bit line has a voltage near the target level, and turns on the precharge transistors when the reference bit line has a voltage below the target level.
公开/授权文献
- US07082069B2 Memory array with fast bit line precharge 公开/授权日:2006-07-25
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