A controlling method of logic operations is used to control a plurality of logics inside a chip, which is in a power peak state. The controlling method comprises the following steps of: providing a control signal to the chip, controlling at least one of the logics based on the control signal at a first timing, and controlling at least another one of the logics based on the control signal at a second timing. The control signal is intent to substantially control actions of the logics synchronously. Moreover, a mainboard and an electronic component, utilizing the controlling method of logic operations, are provided.