A flash memory has an interleaved boot block compatible with multiple processor architectures. The interleaved boot block may include one boot block compatible with a first CPU architecture and another boot block compatible with a second CPU architecture. These two boot blocks may be combined in an interleaved manner in the flash memory so that during a boot process only one of the two boot blocks executes, although both are stored in the flash memory. By interleaving different boot blocks, a common socket computer system capable of supporting multiple processor architectures may be achieved without fully replacing an incompatible basic input/output system (BIOS). Further, the flash memory may contain an updatable portion in which any BIOS segments incompatible with a processor architecture may be updated via a recovery, or update, process.