发明申请
US20060135105A1 Loop filter with gear shift for improved fractional-N PLL settling time
失效
带有换档的环路滤波器,用于改进分数N PLL稳定时间
- 专利标题: Loop filter with gear shift for improved fractional-N PLL settling time
- 专利标题(中): 带有换档的环路滤波器,用于改进分数N PLL稳定时间
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申请号: US11015101申请日: 2004-12-17
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公开(公告)号: US20060135105A1公开(公告)日: 2006-06-22
- 发明人: Henrik Jensen
- 申请人: Henrik Jensen
- 主分类号: H04Q7/20
- IPC分类号: H04Q7/20
摘要:
An integrated circuit radio frequency (RF) transmitter includes a phase locked loop having a multi-mode loop filter that is operable to provide wide band response with a fast settle time in a startup mode of operation and a relatively more narrow response with a longer settle time but with improved filtering in a steady state mode of operation according to one embodiment of the invention. The multi-mode loop filter includes, in one embodiment, selectable resistance circuitry for selecting between a plurality of resistance values based upon a two-state multi-mode control signal to provide the selected resistance values and selectable capacitance circuitry for selecting between a plurality of capacitance values based upon the two-state multi-mode control signal and for operatively coupling selected capacitors to selected resistors to provide the selected capacitance values. As a further aspect of the embodiment of the present invention, the multi-mode loop filter includes buffers for charging non-selected capacitors while not operationally coupled to the multi-mode loop filter to avoid additional settle time for the circuitry.
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