发明申请
US20060145723A1 Voltage level conversion circuit 有权
电压电平转换电路

  • 专利标题: Voltage level conversion circuit
  • 专利标题(中): 电压电平转换电路
  • 申请号: US11175450
    申请日: 2005-07-07
  • 公开(公告)号: US20060145723A1
    公开(公告)日: 2006-07-06
  • 发明人: Hiroshige Hirano
  • 申请人: Hiroshige Hirano
  • 优先权: JP2004-202105 20040708
  • 主分类号: H03K19/094
  • IPC分类号: H03K19/094
Voltage level conversion circuit
摘要:
A voltage level conversion circuit for converting a voltage level of a low voltage system input signal into a voltage level of a high voltage system signal comprises a latch circuit comprising plural high-breakdown-voltage MOS transistors having a high power supply voltage as a breakdown voltage, a first high-breakdown-voltage N channel MOS transistor which discharges one of latch nodes of the latch circuit, and a second high-breakdown-voltage N channel MOS transistor which discharges the other latch node, and a pulse signal obtained by boosting a low voltage system pulse signal is applied to a gate of the first or second high-breakdown voltage N channel MOS transistor when the input signal transits.
公开/授权文献
信息查询
0/0