发明申请
US20060150133A1 Integrated circuit (IC) chip design method, program product and system
失效
集成电路(IC)芯片设计方法,程序产品和系统
- 专利标题: Integrated circuit (IC) chip design method, program product and system
- 专利标题(中): 集成电路(IC)芯片设计方法,程序产品和系统
-
申请号: US11274556申请日: 2005-11-15
-
公开(公告)号: US20060150133A1公开(公告)日: 2006-07-06
- 发明人: Soroush Abbaspour , Gary Ditlow , Chandramouli Kashyap , Ruchir Puri
- 申请人: Soroush Abbaspour , Gary Ditlow , Chandramouli Kashyap , Ruchir Puri
- 主分类号: G06F17/50
- IPC分类号: G06F17/50 ; G06F9/45
摘要:
A circuit design method, computer program product and chip design system embodying the method. A gate selected for static timing analysis (STA) from a circuit design. Initial performance characteristics (e.g., load and transition slew) are determined for the selected gate. A charge equivalent effective capacitance (CQeff) is determined for the gate from the initial performance characteristics. A gate delay is determined in a single pass for the gate using CQeff as an effective load for said selected gate. Optionally, if the total gate load capacitance (Ctot) exceeds CQeff by less than a minimum, the effective capacitance (Ceff) is determined and used for determining the gate delay instead.