发明申请
US20060164364A1 Delay time correction circuit, video data processing circuit, and flat display device
审中-公开
延迟时间校正电路，视频数据处理电路和平板显示设备
- 专利标题： Delay time correction circuit, video data processing circuit, and flat display device
- 专利标题（中）： 延迟时间校正电路，视频数据处理电路和平板显示设备
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申请号： US10564473申请日： 2004-07-27
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公开(公告)号： US20060164364A1公开(公告)日： 2006-07-27
- 发明人: Masaki Murase , Yoshiharu Nakajima , Yoshitoshi Kida
- 申请人： Masaki Murase , Yoshiharu Nakajima , Yoshitoshi Kida
- 优先权： JP2003-280583 20030708; JP2003-347803 20031007
- 国际申请： PCT/JP04/11029 WO 20040727
- 主分类号： G09G3/36
- IPC分类号： G09G3/36
摘要：
The present invention is applied to, for example, a liquid crystal display device having a driving circuit integrally formed on an insulating substrate, and makes it possible to effectively avoid a variation in delay time in a logical circuit using TFTs or the like by inserting dummy data (DD) into input data (D1) and forcedly switching the logical level of the input data (D1) at a predetermined timing during a quiescent period (T2) in which the input data is held at a constant logical level.
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