A multiple-master Inter Integrated Circuit (“I2C) bus system includes a first master device including a first processing device within a first power boundary and a second master device including a second processing device within a second power boundary connected through a single I2C bus to one or more slave devices. The second master device utilizes a software algorithm or hardware component to detect or manage power up of the first power boundary. Additionally, the second master device includes a bus control algorithm that allows it, once initiated, to communicate with the connected slave device, to direct the first power boundary to activate or detect that the first power boundary has powered up, and to release the I2C bus. Once the first processor has initialized, the first master device acquires control of the I2C bus without arbitration or interference with the second master device.