发明申请
- 专利标题: Erase verify for non-volatile memory
- 专利标题(中): 擦除非易失性存储器的验证
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申请号: US11400993申请日: 2006-04-10
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公开(公告)号: US20060181930A1公开(公告)日: 2006-08-17
- 发明人: Christophe Chevallier
- 申请人: Christophe Chevallier
- 专利权人: Micron Technology, Inc.
- 当前专利权人: Micron Technology, Inc.
- 主分类号: G11C11/34
- IPC分类号: G11C11/34
摘要:
A memory device verify system determines a state of memory cells in a memory. The memory includes a memory array having a plurality of memory cells coupled to bit lines. A verify circuit is coupled to the bit lines to determine if memory cells have a erase level that is within predetermined upper and lower limits. The verify circuit can include first and second comparators. In one embodiment, the first comparator is used to compare a bit line current with an upper first reference current. The second comparator is used to compare a bit line current with a lower second reference current. The comparator circuit is not limited to reference currents, but can use reference voltages to compare to a bit line voltage. The verify circuit, therefore, eliminates the need for separate bit line leakage testing to identify over-erased memory cells.