发明申请
- 专利标题: Method of manufacturing semiconductor device and semiconductor device
- 专利标题(中): 制造半导体器件和半导体器件的方法
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申请号: US11346890申请日: 2006-02-03
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公开(公告)号: US20060186548A1公开(公告)日: 2006-08-24
- 发明人: Yoshiyuki Enomoto , Hiroyuki Kawashima , Masaki Okamoto
- 申请人: Yoshiyuki Enomoto , Hiroyuki Kawashima , Masaki Okamoto
- 优先权: JP2005-035414 20050214; JP2005-361211 20051215
- 主分类号: H01L23/52
- IPC分类号: H01L23/52
摘要:
The present invention provides a method of manufacturing a semiconductor device and a semiconductor device that allow use of interlayer and interconnect insulating films having a low dielectric constant in forming a dual damascene structure. A first insulating film, a second insulating film, a first-mask forming layer, a second-mask forming layer, a third-mask forming layer, and a fourth-mask forming layer are sequentially deposited over a substrate. The fourth-mask forming layer is patterned to form a fourth mask having an interconnect trench pattern. After a resist mask is formed on the fourth mask, the layers to the second insulating film are etched to open via holes. The third-mask forming layer is etched through the fourth mask to thereby form a third mask having the interconnect trench pattern and to extend the via holes downward partway across the first insulating film. The second-mask forming layer is etched through the fourth mask to thereby form a second mask having the interconnect trench pattern, and the first insulating film that remains under the bottoms of the via holes is removed. Subsequently, the second insulating film is etched through the second mask to thereby form an interconnect trench, and then the second mask is removed.
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