发明申请
- 专利标题: Switch control apparatus, semiconductor device test apparatus and sequence pattern generating program
- 专利标题(中): 开关控制装置,半导体装置测试装置和序列模式生成程序
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申请号: US11089053申请日: 2005-03-24
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公开(公告)号: US20060208767A1公开(公告)日: 2006-09-21
- 发明人: Hiroyuki Kawashima , Kazushige Yamamoto , Satoshi Shimoyama
- 申请人: Hiroyuki Kawashima , Kazushige Yamamoto , Satoshi Shimoyama
- 申请人地址: JP Tokyo
- 专利权人: Advantest Corporation
- 当前专利权人: Advantest Corporation
- 当前专利权人地址: JP Tokyo
- 优先权: JPJP2004-089022 20040325
- 主分类号: H03K5/19
- IPC分类号: H03K5/19
摘要:
It is an object to properly control timing of opening and closing a switch by a circuit of simple constitution. A switch control apparatus for controlling a switch is provided, the switch control apparatus including a sequence memory for recording a sequence pattern includes open/close instruction data which instruct to open/close the switch thereon; an address control module for sequentially retrieving each of the open/close instruction data of the sequence pattern from the sequence memory; and an open/close state storage module for storing an open/close state instructed by changed open/close instruction data when the open/close instruction data retrieved by the address control module is changed, wherein the switch opens or closes in response to the open/close state stored by the open/close state storage module.
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