发明申请
US20060212686A1 Pipelined instruction processor with data bypassing 有权
流水线指令处理器,数据旁路

Pipelined instruction processor with data bypassing
摘要:
An instruction processing device has a of pipe-line stage with a functional unit for executing a command from an instruction. A first register unit is coupled to the functional unit for storing a result of execution of the command when the command has reached a first one of the pipeline stages, and for supplying bypass operand data to the functional unit. A register file is coupled to the functional unit for storing the result when the command has reached a second one of the pipeline stages, downstream from the first one of the pipeline stages, and for supplying operand data to the functional unit. A disable circuit is coupled to control of the instructions.
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