A multi-chip package includes a first chip group including at least one semiconductor chip on a substrate. The first chip group may be sealed to form a first package body. Connecting test terminals to ball pads allows package-level testing of the first chip group. A second chip group including at least one semiconductor chip may be provided on the first package body. The first package body and the second chip group may be sealed to form a second package body. The multi-chip package may further comprise an interposer substrate provided between the first package body and, for example, the lowest semiconductor chip of the second chip group. The interposer substrate may electrically connect the second chip group to the substrate.