A flip-flop (10) comprises a first latch circuit (18), a second latch circuit (24), and a third latch circuit (26). The first latch circuit (18) is coupled to receive a clock signal and a first power supply voltage. The second latch circuit (24) is coupled to the first latch circuit (18) and receives the clock signal and the first power supply voltage. Preparatory to entering a low power mode, the third latch circuit (26) receives a second power supply voltage and is coupled to the second latch circuit (24) in response to a power down signal. During the low power mode, the first power supply voltage is removed from the first and second latch circuits (18, 24). When returning to a normal operating mode, the first power supply voltage is provided to the first and second latch circuits (18, 24), and the third latch circuit (26) is coupled to the first latch circuit (18) in response to a power restore signal.