- 专利标题: Intelligent timing analysis and constraint generation GUI
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申请号: US11092406申请日: 2005-03-29
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公开(公告)号: US20060230373A1公开(公告)日: 2006-10-12
- 发明人: Juergen Dirks , Martin Fennell , Matthias Dinter
- 申请人: Juergen Dirks , Martin Fennell , Matthias Dinter
- 专利权人: LSI LOGIC CORPORATION
- 当前专利权人: LSI LOGIC CORPORATION
- 主分类号: G06F17/50
- IPC分类号: G06F17/50 ; G06F9/45
摘要:
A system generally including a clock structure analysis tool, a static timing analysis tool and a waveform tool is disclosed. The clock structure analysis tool may be configured to generate a simplified clock structure for a clock signal in a complex clock structure in a design of a circuit. The static timing analysis tool may be configured to generate a plurality of results for a plurality of intermediate signals in the simplified clock structure in response to a static timing analysis of the design. The waveform tool may be configured to generate a first representation in a graphical user interface format of the intermediate signals and the results.
公开/授权文献
- US07523426B2 Intelligent timing analysis and constraint generation GUI 公开/授权日:2009-04-21
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