- 专利标题: Storage control circuit, and method for address error check in the storage control circuit
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申请号: US11236610申请日: 2005-09-28
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公开(公告)号: US20060236205A1公开(公告)日: 2006-10-19
- 发明人: Masahiro Kuramoto , Masao Koyabu , Jun Tsuiki , Junichi Inagaki
- 申请人: Masahiro Kuramoto , Masao Koyabu , Jun Tsuiki , Junichi Inagaki
- 申请人地址: JP Kawasaki
- 专利权人: FUJITSU LIMITED
- 当前专利权人: FUJITSU LIMITED
- 当前专利权人地址: JP Kawasaki
- 优先权: JP2005-100541 20050331
- 主分类号: G11C29/00
- IPC分类号: G11C29/00
摘要:
A method for address error check in a storage control circuit having a storage unit operable to store data in a storage area specified by an address encodes a first code assigned to the address with an even number of bits, encodes a second code assigned to the data written to the storage unit with an odd number of bits, generates a check code based on the first and second codes and stores the check code in the storage unit in correspondence with the data written to the storage unit, and conducts an error check based on data read from the storage unit, a check code corresponding to the data read, and a read address, thus detecting a multi-bit address error.
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