发明申请
US20060247882A1 Test apparatus, test method, electronic device manufacturing method, test simulator and test simulation method
失效
试验装置,试验方法,电子装置制造方法,试验模拟装置及试验模拟方法
- 专利标题: Test apparatus, test method, electronic device manufacturing method, test simulator and test simulation method
- 专利标题(中): 试验装置,试验方法,电子装置制造方法,试验模拟装置及试验模拟方法
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申请号: US11395094申请日: 2006-03-31
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公开(公告)号: US20060247882A1公开(公告)日: 2006-11-02
- 发明人: Hideki Tada , Mitsuo Hori , Takahiro Kataoka , Hiroyuki Sekiguchi
- 申请人: Hideki Tada , Mitsuo Hori , Takahiro Kataoka , Hiroyuki Sekiguchi
- 申请人地址: JP Tokyo
- 专利权人: Advantest Corporation
- 当前专利权人: Advantest Corporation
- 当前专利权人地址: JP Tokyo
- 优先权: JP2005-062044 20050307
- 主分类号: G01R27/28
- IPC分类号: G01R27/28
摘要:
Acceptability of an electronic device is determined with higher precision by performing testing regarding correlation of the timing at which multiple output signals output from the electronic device change. A test apparatus which tests an electronic device by providing test signals to the electronic device and comparing multiple output signals with respective anticipated values, comprises: reference timing detecting means for detecting that one of the output signals has changed; setting means for setting beforehand a minimum time from changing of the output signal to changing of another output signal; acquisition means for acquiring the value of the latter output signal at a timing at which the minimum time has elapsed from detection of change of the former output signal; and determination means for determining the electronic device to be defective in the event that the value of the latter output signal thus acquired does not match the value which the latter output signal should assume following elapsing of the minimum time.
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