发明申请
- 专利标题: METHODS OF FORMING INTEGRATED CIRCUIT ELECTRODES AND CAPACITORS BY WRINKLING A LAYER THAT INCLUDES A HIGH PERCENTAGE OF IMPURITIES
- 专利标题(中): 形成集成电路电容器和电容器的方法,包括一个包含高达百分之百的包层
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申请号: US11462178申请日: 2006-08-03
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公开(公告)号: US20060263977A1公开(公告)日: 2006-11-23
- 发明人: Wan-don Kim , Jae-hyun Joo , Seok-jun Won , Jung-hee Chung , Jin-yong Kim , Suk-jin Chung
- 申请人: Wan-don Kim , Jae-hyun Joo , Seok-jun Won , Jung-hee Chung , Jin-yong Kim , Suk-jin Chung
- 专利权人: Samsung Electronics Co., Ltd.
- 当前专利权人: Samsung Electronics Co., Ltd.
- 优先权: KR10-2006-0067100 20060718
- 主分类号: H01L21/8242
- IPC分类号: H01L21/8242
摘要:
A method of fabricating a uniformly wrinkled capacitor lower electrode without the need to perform a high-temperature heat treatment and a method of fabricating a capacitor including the uniformly wrinkled capacitor lower electrode are provided. A first conductive layer is formed. Then, a second conductive layer including about 20% to about 50% of impurities is formed on the first conductive layer. Next, at least some of the impurities are exhausted from the second conductive layer by heat treating the second conductive layer. A surface of the second conductive layer is wrinkled due to the exhaustion of the impurities from the second conductive layer. A dielectric layer and an upper capacitor electrode may then be formed.