A display panel comprising a pixel array is provided. The pixel array, laid on a first circuit layer, comprises at least one first pixel, at least one second pixel, at least one rescue line, and an isolation layer. The first pixel comprises a thin film transistor aligned to upper edge of the first pixel. The second pixel comprises a thin film transistor aligned to lower edge of the second pixel, wherein the second pixel is adjacent to the first pixel and below the first pixel respectively. The rescue line lay on a second circuit layer, positions at the gap between the first pixel and the second pixel. The isolation layer lies between the first circuit layer and the second circuit layer.