• 专利标题: Integrated circuit conserving power during transitions between normal and power-saving modes
  • 申请号: US11408089
    申请日: 2006-04-21
  • 公开(公告)号: US20060282694A1
    公开(公告)日: 2006-12-14
  • 发明人: Takeshi Ichikawa
  • 申请人: Takeshi Ichikawa
  • 优先权: JP2005-143855 20050517
  • 主分类号: G06F1/00
  • IPC分类号: G06F1/00
Integrated circuit conserving power during transitions between normal and power-saving modes
摘要:
An integrated circuit includes a volatile memory, a central processing unit that normally operates on a first clock, and an input-output circuit that transfers data in synchronization with a second clock having a lower frequency than the first clock. The integrated circuit has a power-saving mode in which the volatile memory loses its data and the central processing unit stops operating. The power-saving mode is preceded and followed by transitional periods during which the central processing unit uses the input-output circuit to save data from the volatile memory to an external memory device and restore the data from the external memory device to the volatile memory. During these transitional periods, the central processing unit operates on the second clock to conserve power.
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