发明申请
- 专利标题： Logic transformation and gate placement to avoid routing congestion
- 专利标题（中）： 逻辑转换和门放置，以避免路由拥塞
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申请号： US11153707申请日： 2005-06-14
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公开(公告)号： US20060282809A1公开(公告)日： 2006-12-14
- 发明人: Chaitra Bhat , M. Chandrika , Atsushi Sugai , Toshihiko Yokota
- 申请人： Chaitra Bhat , M. Chandrika , Atsushi Sugai , Toshihiko Yokota
- 申请人地址： US NY Armonk
- 专利权人： International Business Machines Corporation
- 当前专利权人： International Business Machines Corporation
- 当前专利权人地址： US NY Armonk
- 主分类号： G06F17/50
- IPC分类号： G06F17/50
摘要：
A novel logic design method for avoiding wiring congestion. According to the novel logic design method, an original gate having multiple inputs coming from different directions and having multiple outputs coming to different directions can be transformed to a logic block that has an input stage and an output stage. The gates of the input stage receive signals from the multiple inputs of the original gate. The gates of the output stage send signals to the multiple outputs of the original gate. Each gate of the input stage is placed in a vicinity of its inputs. Each gate of the output stage is placed in a vicinity of its outputs. The gates of the input and output stages are functionally equivalent to the original gate.